54F378 Datasheet | National Semiconductor

Description The ’F378 is a 6-bit register with a buffered mon Enable This device is similar to the ’F174 but with mon Enable rather than mon Master Reset Features Y 6-bit high-speed parallel register Y Positive edge-triggered D-type inputs Y Fully buffered mon clock and enable inputs Y Input clamp diodes limit high-speed termination effects Y Full TTL and CMOS patible mercial 74F378PC 74F378SC (Note 1) 74F378SJ (Note 1) Military 54F378DM (QB) 54F378FM (QB) 54F378LM (QB) Package Number N16E J16A M16A M16D W16A E20A Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9526- 1 IEEE IEC TL F 9526 - 2 TL F 9526 - 3 TL F 9526- 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9526 RRD-B30M75 Printed in U S A Obsolete Unit Loading Fan Out 54F 74F Pin Names Description U L Input IIH IIL HIGH LOW Output IOH IOL E D0 - D5 CP Q0 - Q5 Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Outputs 10 10 10 10 10 10 50 33 3 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b1 m A 20 m A Functional Description The ’F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs The Clock (CP) and Enable (E) inputs are mon to all flip-flops When the E input is LOW new data is entered into the register on the LOW-to-HIGH transition of the CP input When the E input is HIGH the register will retain the present data independent of the CP input Logic Diagram Truth...