The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW
The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH
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54F 74F377 Octal D Flip-Flop with Clock Enable Obsolete May 1995 54F 74F377 Octal D Flip-Flop with Clock Enable General Description The ’F377 has eight edge-triggered D-t...
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lock Enable General Description The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation Features Y Ideal for addressable register applications Y Clock enable for address and data synchronization a
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54F377 Datasheet
