54FCT377 Datasheet - National Semiconductor

Octal D-Type Flip-Flop

54FCT377 Features

* n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’FCT273 for master reset version n See ’FCT373 for transparent latch version n See ’FCT374 for TRI-STATE® version n TTL input and output level compatible n CMOS power co

54FCT377 General Description

The ’FCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-.

54FCT377 Datasheet (148.26 KB)

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54FCT377

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National Semiconductor

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148.26 KB

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Octal d-type flip-flop.

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54FCT377 Octal D-Type Flip-Flop National Semiconductor

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54FCT377 Features

54FCT377 General Description

Datasheet Details

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