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National Semiconductor Electronic Components Datasheet

74F194 Datasheet

4-Bit Bidirectional Universal Shift Register

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November 1994
54F 74F194
4-Bit Bidirectional Universal Shift Register
General Description
The ’F194 is a high-speed 4-bit bidirectional universal shift
register As a high-speed multifunctional sequential build-
ing block it is useful in a wide variety of applications It may
be used in serial-serial shift left shift right serial-parallel
parallel-serial and parallel-parallel data register transfers
The ’F194 is similar in operation to the ’F195 universal shift
register with added features of shift left without external
connections and hold (do nothing) modes of operation
Features
Y Typical shift frequency of 150 MHz
Y Asynchronous master reset
Y Hold (do nothing) mode
Y Fully synchronous serial or parallel data transfers
Commercial
74F194PC
74F194SC (Note 1)
74F194SJ (Note 1)
Military
54F194DM (Note 2)
54F194FM (Note 2)
54F194LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9498–5
TL F 9498 – 1
TL F 9498 – 2
TL F 9498–3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9498
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F194 Datasheet

4-Bit Bidirectional Universal Shift Register

No Preview Available !

Unit Loading Fan Out
Pin
Names
S0 S1
P0 – P3
DSR
DSL
CP
MR
Q0 – Q3
Description
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Functional Description
The ’F194 contains four edge-triggered D flip-flops and the
necessary interstage logic to synchronously perform shift
right shift left parallel load and hold operations Signals
applied to the Select (S0 S1) inputs determine the type of
operation as shown in the Mode Select Table Signals on
the Select Parallel data (P0 – P3) and Serial data (DSR DSL)
inputs can change when the clock is in either state provid-
ed only that the recommended setup and hold times with
respect to the clock rising edge are observed A LOW sig-
nal on Master Reset (MR) overrides all other inputs and
forces the outputs LOW
Mode Select Table
Operating
Mode
Reset
Inputs
Outputs
MR S1 S0 DSR DSL Pn Q0 Q1 Q2
L XX X
X XLLL
Hold
H l l X X X q0 q1 q2
Shift Left
Hhl
Hhl
X
X
l X q1 q2 q3
h X q1 q2 q3
Shift Right
H lh
l
H lh h
X X L q0 q1
X X H q0 q1
Parallel Load
H
h
h
X
X pn p0 p1 p2
H (h) e High Voltage Level
L (l) e Low Voltage Level
pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition
X e Immaterial
Logic Diagram
Q3
L
q3
L
H
q2
q2
p3
TL F 9498 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F194
Description 4-Bit Bidirectional Universal Shift Register
Maker National Semiconductor
Total Page 8 Pages
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