Unit Loading Fan Out
Pin Names
S
OE
I0a – I0d
I1a – I1d
Za – Zd
Description
Common Data Select Input
TRI-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
TRI-STATE Inverting Data Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Functional Description
The ’F258A is a quad 2-input multiplexer with TRI-STATE
outputs It selects four bits of data from two sources under
control of a common Select input (S) When the Select input
is LOW the I0x inputs are selected and when Select is
HIGH the I1x inputs are selected The data on the selected
inputs appears at the outputs in inverted form The ’F258A
is the logic implementation of a 4-pole 2-position switch
where the position of the switch is determined by the logic
levels supplied to the Select input The logic equation for
the outputs is shown below
Zn e OE (I1n S a I0n S)
When the Output Enable input (OE) is HIGH the outputs are
forced to a high impedance OFF state If the outputs of the
TRI-STATE devices are tied together all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings Designers should
ensure that Output Enable signals to TRI-STATE devices
whose outputs are tied together are designed so there is no
overlap
Truth Table
Output
Enable
OE
H
L
L
L
L
Select
Input
S
X
H
H
L
L
Data
Inputs
I0 I1
XX
XL
XH
LX
HX
Output
Z
Z
H
L
H
L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
Logic Diagram
TL F 9508 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
