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74F374 Datasheet

Octal D-Type Flip-Flop with TRI-STATE Outputs

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May 1995
54F 74F374
Octal D-Type Flip-Flop with TRI-STATE Outputs
General Description
The ’F374 is a high-speed low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications A buff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops
Features
Y Edge-triggered D-type inputs
Y Buffered positive edge-triggered clock
Y TRI-STATE outputs for bus-oriented applications
Y Guaranteed 4000V minimum ESD protection
Commercial
74F374PC
74F374SC (Note 1)
74F374SJ (Note 1)
74F374MSA (Note 1)
Military
54F374DM (QB)
54F374FM (QB)
54F374LM (QB)
Package
Number
N20A
J20A
M20B
M20D
MSA20
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
SOIC SSOP and Flatpak
Pin Assignment
for LCC
TL F 9524–1
IEEE IEC
TL F 9524 – 2
TL F 9524 – 3
TL F 9524–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9524
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F374 Datasheet

Octal D-Type Flip-Flop with TRI-STATE Outputs

No Preview Available !

Unit Loading Fan Out
Pin
Names
Description
54F 74F
UL
HIGH LOW
Input IIH IIL
Output IOH IOL
D0 – D7
CP
OE
O0 – O7
Data Inputs
Clock Pulse Input (Active Rising Edge)
TRI-STATE Output Enable Input (Active LOW)
TRI-STATE Outputs
10 10
10 10
10 10
150 40 (33 3)
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Functional Description
The ’F374 consists of eight edge-triggered flip-flops with in-
dividual D-type inputs and TRI-STATE true outputs The
buffered clock and buffered Output Enable are common to
all flip-flops The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition With
the Output Enable (OE) LOW the contents of the eight flip-
flops are available at the outputs When the OE is HIGH the
outputs go to the high impedance state Operation of the
OE input does not affected the state of the flip-flops
Truth Table
Inputs
Dn CP OE
HL
L
LL L
XXH
Internal
Register
H
L
X
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
L e LOW-to-HIGH Clock Transition
Output
On
H
L
Z
Logic Diagram
TL F 9524 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F374
Description Octal D-Type Flip-Flop with TRI-STATE Outputs
Maker National Semiconductor
Total Page 8 Pages
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