Datasheet4U Logo Datasheet4U.com

74F377 - Octal D Flip-Flop

Download the 74F377 datasheet PDF. This datasheet also covers the 74F377PC variant, as both devices belong to the same octal d flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH

Key Features

  • Y Ideal for addressable register.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74F377PC_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74F377 Octal D-Type Flip-Flop Fairchild
74F377A Octal D-type flip-flop Philips
74F377A OCTAL D-TYPE FLIP-FLOP Texas Instruments
74F37 Quad 2-input NAND buffer Philips
74F37 Quad Two-Input NAND Buffer Fairchild

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
74F374 Octal D-Type Flip-Flop
74F378 Parallel D Register
74F32 Quad 2-Input OR Gate
74F38 Quad Two-Input NAND Buffer
74F382 4-Bit Arithmetic Logic

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
54F 74F377 Octal D Flip-Flop with Clock Enable May 1995 54F 74F377 Octal D Flip-Flop with Clock Enable General Description The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation Features Y Ideal for addressable register applications Y Clock enable for address and data synchronization applications Y Eight edge-triggered D flip-flops Y Buffered common clock Y S