74F377 Datasheet | Fairchild Semiconductor

74F377 Octal D-Type Flip-Flop with Clock Enable April 1988 Revised August 1999 74F377 Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features s Ideal for addressable register...