74F377A Overview
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered.
74F377A Key Features
- High impedance inputs for reduced loading (20µA in Low and
- Ideal for addressable register

