74F377A
Overview
The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
- High impedance inputs for reduced loading (20µA in Low and
- Ideal for addressable register applications
- Enable for address and data synchronization applications
- Eight edge-triggered D-type flip-flops
- Buffered common clock
- See ’F273A for Master Reset version
- See ’F373 for transparent latch version
- See ’F374 for 3-State version
