Y Y Y Y Y Y Y Y LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs In.

include Buffer storage registers Shift registers Pattern generators Typical clock frequency 40 MHz Typical power dissipa.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the set.

74LS171

74LS173

74LS174

74LS10

74LS107

74LS109

74LS109A

74LS11

74LS112

74LS112A

74LS114A

74LS12

74LS121