74LS257B Datasheet PDF - National Semiconductor Quad 2-Data Selectors/Multiplexers Specs

74LS257B - Quad 2-Data Selectors/Multiplexers

This page provides the datasheet information for the 74LS257B, a member of the 74LS258B Quad 2-Data Selectors/Multiplexers family.

Datasheet Summary

Description

These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the common outputs disabled (at a high impedance state) the low impedance of the single enabled output will drive the bus line to a

Features

Y TRI-STATE versions LS157 and LS158 with same pinouts Y Schottky-clamped for significant improvement in A-C performance Y Provides bus interface from multiple sources in highperformance systems Y Average propagation delay from data input 12 ns Y Typical power dissipation LS257B 50 mW LS258B 35 mW Y Alternate military aerospace devices (54LS257A 54LS258A) are available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagrams Dual-In-Line Package Dual-In-.

Datasheet Details

Part number	74LS257B
Manufacturer	National Semiconductor
File Size	154.51 KB
Description	Quad 2-Data Selectors/Multiplexers
Datasheet	74LS257B Datasheet
Additional preview pages of the 74LS257B datasheet.

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Full PDF Text Transcription

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54LS257A DM54LS257B DM74LS257B 54LS258A DM54LS258B DM74LS258B TRI-STATE Quad 2-Data Selectors Multiplexers June 1989 54LS257A DM54LS257B DM74LS257B 54LS258A DM54LS258B DM74LS258B TRI-STATE Quad 2-Data Selectors Multiplexers General Description These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the common outputs disabled (at a high impedance state) the low impedance of the single enabled output will drive the bus line to a high or low logic level To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels the output enable circuitry is designed such that the output disable times are shorter than the output enable times This TRI-

Published: May 11, 2022 |