ADC10221 Datasheet | National Semiconductor

ADC10221 10-Bit, 15 MSPS, 98 m W A/D Converter with Internal Sample and Hold January 2000 ADC10221 10-Bit, 15 MSPS, 98 m W A/D Converter with Internal Sample and Hold General Description The ADC10221 is the first in a family of low power, high performance CMOS analog-to-digital converters. It can digitize signals to 10 bits resolution at sampling rates up to 20 MSPS (15 MSPS guaranteed) while consuming a typical 98 m W from a single 5V supply. Reference force and sense pins allow the user to connect an external reference buffer amplifier to ensure optimal accuracy. The ADC10221 is guaranteed to have no missing codes over the full operating temperature range. The unique two stage architecture achieves 9.2 Effective Bits with a 10MHz input signal and a 20MHz clock frequency. Output formatting is straight binary coding. To ease interfacing to 3V systems, the digital I/O power pins of the ADC10221 can be tied to a 3V power source, making the outputs 3V patible. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power standby state, where it typically consumes less than 4 m W. The ADC10221’s speed, resolution and single supply operation make it well suited for a variety of applications in video, imaging, munications, multimedia and high speed data acquisition. Low power, single supply operation ideally suit the ADC10221 for high speed portable applications, and its speed and resolution are ideal for charge coupled device (CCD) input systems. The ADC10221 es in a space saving 32-pin TQFP and operates over the industrial (- 40˚C ≤ TA ≤ +85˚C) temperature range. Features n n n n n Internal Sample-and-Hold Single +5V Operation Low Power Standby Mode Guaranteed No Missing Codes TTL/CMOS or 3V Logic Input/Output patible Key Specifications n Resolution n Conversion Rate n ENOB 10 MHz Input, 20 MHz Clock n DNL n Power Consumption n Low Power Standby Mode 9.2 Bits (typ) 0.35 LSB (typ) 98 m W...