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National Semiconductor Electronic Components Datasheet

DM54LS109A Datasheet

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs

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DM54LS109A pdf
June 1989
54LS109 DM54LS109A DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock The data on the J and K inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs
Features
Y Alternate Military Aerospace device (54LS109) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6368 – 1
Order Number 54LS109DMQB 54LS109FMQB DM54LS109AJ
DM54LS109AW DM74LS109AM or DM74LS109AN
See NS Package Number J16A M16A N16E or W16A
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
LH
X
XX
H
L
HL
X
XX
L
H
LL
X XX H
H
H H u LL L H
H H u HL
Toggle
uH H
L H Q0
Q0
H H u HH H L
HH
L
X X Q0
Q0
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
u e Rising Edge of Pulse
e This configuration is nonstable that is it will not persist when preset
and or clear inputs return to their inactive (high) state
Q0 e The output logic level of Q before the indicated input conditions were
established
Toggle e Each output changes to the complement of its previous level on
each active transition of the clock pulse
C1995 National Semiconductor Corporation TL F 6368
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

DM54LS109A Datasheet

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs

No Preview Available !

DM54LS109A pdf
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
Parameter
DM54LS109A
Min Nom Max
VCC
VIH
VIL
IOH
IOL
fCLK
fCLK
tW
Supply Voltage
45 5 55
High Level Input Voltage
2
Low Level Input Voltage
07
High Level Output Current
b0 4
Low Level Output Current
4
Clock Frequency (Note 2)
0
25
Clock Frequency (Note 3)
0
20
Pulse Width
(Note 2)
Clock High
Preset Low
18
15
Clear Low
15
tW
Pulse Width
Clock High
25
(Note 3)
Preset Low
20
Clear Low
20
utSU
Setup Time
Data High
30
(Notes 1 2)
Data Low
20u
utSU
Setup Time
Data High
35
(Notes 1 3)
Data Low
25u
tH Hold Time (Note 4)
0u
TA
Free Air Operating Temperature
b55
uNote 1 The symbol ( ) indicates the rising edge of the clock pulse is used for reference
Note 2 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 4 TA e 25 C and VCC e 5V
125
DM74LS109A
Min Nom Max
4 75 5 5 25
2
08
b0 4
8
0 25
0 20
18
15
15
25
20
20
30u
20u
35u
25u
0u
0 70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
C
2


Part Number DM54LS109A
Description Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs
Maker National Semiconductor
Total Page 6 Pages
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