Y Y Y Y Y Y Complementary outputs Direct overriding (data) inputs Gated clock inputs Parallel-to-serial data conversion Typical frequency 35 MHz Typical power dissipatio.

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in access is made available by eight individual direct data inputs which are enabled by a low level at the shift load input These r.

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