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DM54LS165 - 8-Bit Parallel In/Serial Output Shift Registers

Description

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in access is made available by eight individual direct data inputs which are enabled by a low level at the shift load input These registers also feature gated clock inputs and compl

Features

  • Y Y Y Y Y Y Complementary outputs Direct overriding (data) inputs Gated clock inputs Parallel-to-serial data conversion Typical frequency 35 MHz Typical power dissipation 105 mW Connection Diagram Dual-In-Line Package TL F 6399.
  • 1 Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N See NS Package Number J16A M16B N16E or W16A Function Table Inputs Shift Load L H H H H Clock Inhibit X L L L H Clock X L Serial X X H L X Parallel A H a h X X X X QA a QA0 H L QA0 Internal Out.

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DM54LS165 DM74LS165 8-Bit Parallel In Serial Output Shift Registers May 1992 DM54LS165 DM74LS165 8-Bit Parallel In Serial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in access is made available by eight individual direct data inputs which are enabled by a low level at the shift load input These registers also feature gated clock inputs and complementary outputs from the eighth bit Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock-inhibit function Holding either of the clock inputs high inhibits clocking and holding either clock input low with the load input high enables the other clock input The clock-inhibit input should be ch
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