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National Semiconductor Electronic Components Datasheet

DM54LS165 Datasheet

8-Bit Parallel In/Serial Output Shift Registers

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DM54LS165 pdf
May 1992
DM54LS165 DM74LS165 8-Bit Parallel
In Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of QA toward QH when clocked Parallel-in ac-
cess is made available by eight individual direct data inputs
which are enabled by a low level at the shift load input
These registers also feature gated clock inputs and comple-
mentary outputs from the eighth bit
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a clock-inhibit function Hold-
ing either of the clock inputs high inhibits clocking and hold-
ing either clock input low with the load input high enables
the other clock input The clock-inhibit input should be
changed to the high level only while the clock input is high
Parallel loading is inhibited as long as the load input is high
Data at the parallel inputs are loaded directly into the regis-
ter on a high-to-low transition of the shift load input regard-
less of the logic levels on the clock clock inhibit or serial
inputs
Features
Y Complementary outputs
Y Direct overriding (data) inputs
Y Gated clock inputs
Y Parallel-to-serial data conversion
Y Typical frequency 35 MHz
Y Typical power dissipation 105 mW
Connection Diagram
Dual-In-Line Package
TL F 6399 – 1
Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N
See NS Package Number J16A M16B N16E or W16A
Function Table
Shift
Load
Clock
Inhibit
Inputs
Clock
Serial
Parallel
AH
Internal
Outputs
QA QB
L X X X ah a b
H L LX
H L uH
H L uL
HH XX
X
QA0
QB0
X H QAn
X L QAn
X
QA0
QB0
H e High Level (steady state) L e Low Level (steady state)
X e Don’t Care (any input including transitions)
u e Transition from low-to-high level
a h e The level of steady-state input at inputs A through H respectively
QA0 QB0 QH0 e The level of QA QB or QH respectively before the indicated steady-state input conditions were established
uQAn QGn e The level of QA or QG respectively before the most recent transition of the clock
Output
QH
h
QH0
QGn
QGn
QH0
C1995 National Semiconductor Corporation TL F 6399
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

DM54LS165 Datasheet

8-Bit Parallel In/Serial Output Shift Registers

No Preview Available !

DM54LS165 pdf
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
fCLK
tW
tSU
tH
TA
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
Pulse Width
(Note 2)
Setup Time
(Note 6)
Hold Time (Note 6)
Free Air Operating Temperature
Clock
Load
Parallel
Serial
Enable
Shift
DM54LS165
Min Nom Max
45 5 55
2
07
b0 4
4
30
18
15
10
10
10
10
5
b55
125
DM74LS165
Min Nom Max
4 75 5
5 25
2
08
b0 4
8
0 25
0 20
25
15
10
20
30
45
0
0 70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 3)
Max
Units
VI
VOH
Input Clamp Voltage
High Level Output
Voltage
VCC e Min II e b18 mA
VCC e Min IOH e Max
VIL e Max VIH e Min
DM54
DM74
b1 5
V
25
27 34
V
VOL
Low Level Output
VCC e Min IOL e Max
Voltage
VIL e Max VIH e Min
DM54
DM74
04
0 35 0 5 V
IOL e 4 mA VCC e Min
II Input Current Max VCC e Max VI e 7V (DM74) Shift Load
Input Voltage
VI e 10V (DM54)
Others
0 25 0 4
0 3 mA
01
IIH
High Level Input
VCC e Max
Current
VI e 2 7V
Shift Load
Others
60 mA
20
IIL
Low Level Input
VCC e Max
Current
VI e 0 4V
Shift Load
Others
b1 2
b0 4
mA
IOS Short Circuit
Output Current
VCC e Max
(Note 4)
DM54
DM74
b20
b20
b100
b100
mA
ICC Supply Current
VCC e Max (Note 5)
21 36 mA
Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 All typicals are at VCC e 5V TA e 25 C
Note 4 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 5 With all outputs open clock inhibit and shift load at 4 5V and a clock pulse applied to the CLOCK input ICC is measured first with the parallel inputs at
4 5V then again grounded
Note 6 TA e 25 C and VCC e 5V
2


Part Number DM54LS165
Description 8-Bit Parallel In/Serial Output Shift Registers
Maker National Semiconductor
Total Page 6 Pages
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