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DM54LS42 - BCD/Decimal Decoders

General Description

These BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of input logic ensures that all outputs remain off for all invalid (10 15) input condition

Key Features

  • Y Diode clamped inputs Y Also for.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders June 1989 54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders General Description These BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions Connection Diagram Dual-In-Line Package TL F 6365 – 1 Order Number 54LS42DMQB 54LS42FMQB DM54LS42J DM54LS42W DM74LS42M or DM74LS42N See NS Package Number J16A M16A N16E or W16A Logic Diagram Features Y Diode clamped inputs Y Also for applications as 4-line-to-16-line decoders 3line-to-8-line decoders Y All outputs are high for invalid input conditions Y Alternate Military Aeros