Datasheet4U Logo Datasheet4U.com

DS90C383 - +3.3V Programmable LVDS Transmitter

General Description

The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • n 20 to 65 MHz shift clock support n Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption < 250 mW (typ) n Power-down mode (< 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. n Up to 227 Megabytes/sec bandwidth n Up to 1.8 Gbps throughput n Narrow bus reduces cable size and cost n 290 mV swing LVDS devices for low EMI n PLL requires no external c.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DS90C383B Programmable LVDS Transmitter Texas Instruments
DS90C385A +3.3V Programmable LVDS Transmitter Texas Instruments
DS90C387 Dual Pixel LVDS Display Interface Texas Instruments
DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter Texas Instruments
DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter Texas Instruments

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
DS90C383A +3.3V Programmable LVDS Transmitter
DS90C385 +3.3V Programmable LVDS Transmitter
DS90C387 Dual Pixel LVDS Display Interface
DS90C387A Dual Pixel LVDS Display Interface/FPD-Link
DS90C363 +3.3V Programmable LVDS Transmitter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD) Link—65 MHz November 2000 DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/ LVTTL data.