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DS90UR241Q - 5-43 MHz DC-Balanced 24-Bit FPD-Link Serializer/Deserializer

Download the DS90UR241Q datasheet PDF. This datasheet also covers the DS90UR124Q variant, as both devices belong to the same 5-43 mhz dc-balanced 24-bit fpd-link serializer/deserializer family and are provided as variant models within a single manufacturer datasheet.

Description

The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information.

Features

  • pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK.
  • 24:1 interface compression.
  • Embedded clock with DC Balancing supports AC-coupled data transmission.
  • Capable to drive up to 10 meters shielded twisted-pair.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90UR124Q_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90UR241Q/DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset www.DataSheet4U.com DS90UR241Q DS90UR124Q September 4, 2009 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18bit color depth - RGB666 + HS, VS, DE + 3 additional general purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths.
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