DS90UR241-Q1 Overview
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPDLink II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional generalpurpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. RAOFF Block Diagram REN Input Latch DC Balance Encoder Parallel to Serial RT = 100: RT = 100: Serial to Parallel DC Balance Decoder
DS90UR241-Q1 Key Features
- 1 Supports Displays With 18-Bit Color Depth
- 5-MHz to 43-MHz Pixel Clock
- Automotive-Grade Product AEC-Q100 Grade 2 Qualified
- 24:1 Interface pression
- Embedded Clock With DC Balancing Supports AC-Coupled Data Transmission
- Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
- No Reference Clock Required (Deserializer)
- Meets ISO 10605 ESD
- Greater than 8 kV HBM ESD Structure
- Hot Plug Support