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DS99R101 (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101 Description

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.DataSheet4U.com DS99R101/DS99R102 3-40MHz DC-Balance.
The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock informatio.

DS99R101 Features

* 3 MHz
* 40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions Transmitter and Receiver
* User selectable clock edge for parallel data on both coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embed

DS99R101 Applications

* LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects All LVCMOS inputs and control pins have internal pulldown On-chip filters for PLLs on Transmitter a

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Datasheet Details

Part number
DS99R101
Manufacturer
National Semiconductor
File Size
938.07 KB
Datasheet
DS99R101_NationalSemiconductor.pdf
Description
(DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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📌 All Tags

DS99R101 DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer National Semiconductor
National Semiconductor DS99R101-like datasheet