Datasheet Details
| Part number | DS99R101 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 400.41 KB |
| Description | 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer |
| Datasheet |
 DS99R101 Datasheet
|
|
|
General Description
The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Key Features
- 1.
- 2 3 MHz.
- 40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions.
- User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver.
- Internal DC Balancing Encode/Decode.
- Supports AC-Coupling Interface with No External Coding Required.
- Individual Power-Down Controls for Both Transmitter and Receiver.
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed.
