DS99R101
Description
The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Key Features
- User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
- Internal DC Balancing Encode/Decode - Supports AC-Coupling Interface with No External Coding Required
- Individual Power-Down Controls for Both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed
- All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
- Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
- PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
- All LVCMOS Inputs and Control Pins Have Internal Pulldown
- On-Chip Filters for PLLs on Transmitter and Receiver
