DS99R101 Overview
The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector...
DS99R101 Key Features
- User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
- Internal DC Balancing Encode/Decode
- Supports AC-Coupling Interface with No External Coding Required
- Individual Power-Down Controls for Both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed
- All Codes RDL (Random Data Lock) to Support Live-Pluggable
DS99R101 Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
