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DS99R102 - 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer

This page provides the datasheet information for the DS99R102, a member of the DS99R101 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer family.

Description

The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Features

  • 1.
  • 2 3 MHz.
  • 40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions.
  • User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver.
  • Internal DC Balancing Encode/Decode.
  • Supports AC-Coupling Interface with No External Coding Required.
  • Individual Power-Down Controls for Both Transmitter and Receiver.
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed.

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Datasheet preview – DS99R102

Datasheet Details

Part number DS99R102
Manufacturer Texas Instruments
File Size 400.41 KB
Description 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer
Datasheet download datasheet DS99R102 Datasheet
Additional preview pages of the DS99R102 datasheet.

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Other Datasheets by Texas Instruments
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DS99R101, DS99R102 www.ti.
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