The DS99R105/DS99R106 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Features
1.
2 3 MHz.
40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions.
Capable to Drive Shielded Twisted-Pair Cable.
User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver.
Internal DC Balancing Encode/Decode.
Supports AC-Coupling Interface with no External Coding Required.
Individual Power-Down Controls for Both Transmitter and Receiver.
Embedded Clock CDR (Clock and Data Recovery) on Receiv.
DS99R105 Datasheet
