DS99R105 deserializer equivalent, (ds99r105 / ds99r106) 3-40mhz dc-balanced 24-bit lvds serializer and deserializer.
pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
* Interna.
LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side.
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by elimi.
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