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INS8250-B - Asynchronous Receiver/Transmitter

Download the INS8250-B datasheet PDF. This datasheet also covers the INS8250 variant, as both devices belong to the same asynchronous receiver/transmitter family and are provided as variant models within a single manufacturer datasheet.

Description

Each of these parts function as a serial data input/output interface in a microcomputer system.

The system software determines the functional configuration of the UART via a TRI-STATE® 8-bit bidirectional data bus.

Features

  • Easily interfaces to most popular microprocessors.
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data stream.
  • Holding and shift registers eliminate the need for pre­ cise synchronization between the CPU and the serial data.
  • Independently controlled transmit, receive, line status, and data set interrupts.
  • Programmable baud generator allows division of any in­ put clock by 1 to (216 - 1) and generates the internal.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (INS8250_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
INS8250/INS8250-B National Sem iconductor INS8250, INS8250-B Universal Asynchronous Receiver/Transmitter General Description Each of these parts function as a serial data input/output interface in a microcomputer system. The system software determines the functional configuration of the UART via a TRI-STATE® 8-bit bidirectional data bus. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters re­ ceived from the CPU. The CPU can read the complete status of the UART. Status information reported includes the type and condition of the transfer operations being per­ formed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt).
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