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National Semiconductor Electronic Components Datasheet

PC87415 Datasheet

PCI-IDE DMA Master Mode Interface Controller

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PRELIMINARY
March 1996
PC87415
PCI-IDE DMA Master Mode Interface Controller
1 0 General Description
The Enhanced PCI-IDE Interface is a single-chip controller
packaged in a 100-pin PQFP It provides 2 IDE channels for
interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM
directly on the PCI Local bus An enhanced DMA controller
on-chip increases system performance by providing full
scatter gather data transfers between IDE devices and sys-
tem memory without CPU intervention Four levels of both
write posting and read prefetching per channel allow the
host CPU to run concurrently with IDE cycles Programma-
ble timing functions provide maximum flexibility of timing pa-
rameters per drive for optimizing the data transfer rate per
drive Both PC compatible addressing and PCI compliant
addressing are supported by re-mapping the base address-
es A power control feature allows turning off power to the
IDE cables
The Enhanced PCI-IDE Interface connection to the PCI bus
is virtually ‘‘glue-less’’ with only one additional TTL data
buffer (optional) This high-integration solution reduces
component count eases board design reduces cost and
increases reliability
The Enhanced PCI-IDE supports faster ATA devices using
PIO modes 1 2 3 and 4 as well as DMA modes 0 1 and 2
It comes with a full suite of software drivers for DOS 5 0 –
6 x Windows 3 x Windows 95 Windows NTTM OS 2
2 x Novell NetWareTM 3 1x – 4 x and SCO UNIX 3 x
TRI-STATE is a registered trademark of National Semiconductor Corporation
WATCHDOGTM is a trademark of National Semiconductor Corporation
Novell is a registered trademark of Novell Inc
NetWareTM is a trademark of Novell Inc
Unix is a registered trademark of AT T Bell Laboratories
Windows and Windows 95 are registered trademarks of Microsoft Corporation
Windows NTTM is a trademark of Microsoft Corporation
2 0 Features
Y PCI bus interface for up to 4 IDE devices
Y 33 MHz 32-bit PCI bus data path with full parity error
reporting
Y 16 7 MByte sec maximum IDE transfer rate
Y Support for 2 IDE channels ( 2 IDE devices per chan-
nel)
Y Primary or secondary IDE addressing (1F0x 170x) in
PC compatible mode
Y Re-mappable base registers for full PCI compliance
Y Concurrent channel operation (PIO DMA modes)
Y 4 Double Word write FIFO per channel
Y 4 Double Word read prefetch FIFO per channel
Y Enhanced DMA mode with scatter gather capability
Y ANSI ATA Modes 0 through 4 PIO support (internal
DMA not selected)
Y IORDY handshaking for PIO
Y ANSI ATA Modes 0 through 2 Multiword DMA support
(internal DMA selected)
Y Individually programmable command and recovery tim-
ing for reads and writes per channel drive for com-
mand control and data
Y Individually programmable data sector size for read pre-
fetches per channel
Y PC compatible interrupt routing of IRQ14 and IRQ15
Y Hardware and software chip enable disable
Y Optional Power Control for IDE Drives
Y Fully static logic design
Y 100-pin PQFP package
FIGURE 1 The PC87415 in a PCI Based System
C1996 National Semiconductor Corporation TL F 12497
RRD-B30M46 Printed in U S A
TL F 12497 – 1
http www national com


National Semiconductor Electronic Components Datasheet

PC87415 Datasheet

PCI-IDE DMA Master Mode Interface Controller

No Preview Available !

Table of Contents
1 0 GENERAL DESCRIPTION
2 0 FEATURES
3 0 SYSTEM DIAGRAM
4 0 PIN DESCRIPTION
4 1 PCI Interface
4 2 IDE Interface
4 3 Power Control
4 4 Power and Ground
4 5 Pinout
5 0 CONFIGURATION REGISTERS
6 0 BUS MASTER IDE CONTROL AND STATUS
REGISTERS
7 0 FUNCTIONAL DESCRIPTION
7 1 PCI Interface
7 1 1 Commands
7 1 2 Termination
7 1 2 1 Target Abort in Target Mode
7 1 2 2 Retry in Target Mode
7 1 2 3 Target Abort in Master Mode
7 1 2 4 Retry in Master Mode
7 1 2 5 Disconnect in Master Mode
7 1 2 6 Master Abort in Master Mode
7 2 Data Buffers
7 2 1 Write Posting
7 2 2 Prefetch
7 2 3 Two Channel Buffer Protocol
7 3 IDE Interface
7 3 1 IDE Protocol
7 3 1 1 PIO Single Sector Reads
7 3 1 2 PIO Block Mode Reads
7 3 1 3 PIO Single Sector Writes
7 3 1 4 PIO Block Mode Writes
7 3 1 5 DMA Mode
7 3 2 Independent Timing per Drive
7 3 3 Flow Control
7 3 3 1 PIO
7 3 3 1 1 IORDY
7 3 3 1 2 Pseudo DMA
7 3 3 2 DMA
7 3 4 Interrupt Routing
7 3 5 Prefetching
7 3 6 Legacy Native Mapping Scheme
http www national com
7 0 FUNCTIONAL DESCRIPTION (Continued)
7 4 DMA Controller
7 4 1 DMA Engine
7 4 1 1 Alignment
7 4 2 DMA Engine Protocol
7 4 2 1 Scenario 1
7 4 2 1 1 Bus Master Writes
7 4 2 1 2 Bus Master Reads
7 4 2 2 Scenario 2
7 4 2 2 1 Bus Master Writes
7 4 2 2 2 Bus Master Reads
7 4 2 3 Scenario 3
7 4 2 3 1 Bus Master Writes
7 4 2 3 2 Bus Master Reads
7 4 2 4 PCI Bus Request
7 4 2 4 1 PCI Master Reads
7 4 2 4 2 PCI Master Writes
7 4 3 Master Aborts
7 4 4 Target Aborts
7 4 5 Data Synchronization
7 4 5 1 Normal
7 4 5 2 Byte Count is Less than IDE transfer
size
7 4 5 3 Byte Count is Greater than IDE transfer
size
7 4 5 4 Transfer in Progress
7 4 6 Bus Master Programming Sequence
8 0 ELECTRICAL CHARACTERISTICS
8 1 Absolute Maximum Ratings
8 2 Recommended Operating Conditions
8 3 DC Electrical Characteristics
8 4 AC Timing Specifications
8 4 1 PCI Timing Specifications
8 4 2 ATA IDE Timing Specifications
8 4 3 Configuration Register Read Cycles
8 4 4 Configuration Register Write Cycles
8 4 5 Prefetch Cycles (Read Buffer Empty)
8 4 6 Prefetch Cycles (Read Buffer Not Empty)
8 4 7 Posted Write Cycles (Medium Decode)
8 4 8 Posted Write Cycles (Fast Decode)
8 4 9 IDE Non Data Read Cycles
8 4 10 IDE Non Data Write Cycles
8 4 11 DMA Cycles
9 0 APPLICATION INFORMATION
9 1 Power Control for IDE Drives
9 2 Native Mode Interrupt Support
9 3 DMA Bus Master Control Status Register
10 0 ERRATA
10 1 Target Mode
2


Part Number PC87415
Description PCI-IDE DMA Master Mode Interface Controller
Maker National Semiconductor
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PC87415 Datasheet PDF






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