ML87V2103
Overview
PEDL87V2103DIGEST-01 Issue Date: Jan. 20, 2003 Preliminary Video Signal Noise Reduction and Rate Conversion IC with a Built-in 3.9 Mbit Field Memory The ML87V2103 comprises a 3.9 Mbit field memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise and double the conversion speed.
- Built-in memory: 3.9 Mbit filed memory × 1 unit
- Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656): 14.75/29.5 MHz
- Maximum output operating frequency: 29.5 MHz (double-speed conversion)
- Power supply voltage : 3.3 V ± 0.3 V
- Input pin: TTL-5V tolerant (5 V withstand voltage)
- Input/output pins: Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage)
- Output pin: LVCMOS (3.3 V)
- Input data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2) YCbCr (8 bits (YCbCr)) (4:2:2) ITU-R BT.656 (8 bits (YCbCr))
- Output data format: YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
- Serial bus: I2C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps)
