sp;–32
  –1 Nishi
  –Gotanda, Shinagawa
  –ku, Tokyo, Japan 141
  –8549 Phone: 81
  –3
  –54.

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each cus.

The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is t.

7427

74279

7420

7421

74221

7423

74240

74244

74245

74247

74248

7425

74251