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FIN1002 - High-Speed Differential Reciever

General Description

This single receiver is designed for high

utilizing Low Voltage Differential Signaling (LVDS) technology.

The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.

Key Features

  • Greater than 400 Mbs Data Rate.
  • 3.3 V Power Supply Operation.
  • 0.4 ns Maximum Pulse Skew.
  • 2.5 ns Maximum Propagation Delay.
  • Bus Pin ESD (HBM) Protection Exceeds 10 kV.
  • Power.
  • Off, Over.
  • voltage Tolerant Input and Output.
  • Fail.
  • safe Protection for open.
  • circuit and Non.
  • driven, Shorted, or Terminated Conditions.
  • High.
  • impedance Output at VCC < 1.5 V.
  • Meets or exceeds TIA/EIA.

📥 Download Datasheet

Datasheet Details

Part number FIN1002
Manufacturer onsemi
File Size 226.10 KB
Description High-Speed Differential Reciever
Datasheet download datasheet FIN1002 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LVDS 1-Bit, High-Speed Differential Reciever FIN1002 Description This single receiver is designed for high−speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high−speed transfer of clock or data. The FIN1002 can be paired with its companion driver, the FIN1001, or with any other LVDS driver. Features • Greater than 400 Mbs Data Rate • 3.3 V Power Supply Operation • 0.4 ns Maximum Pulse Skew • 2.