FIN1002 Datasheet | Fairchild Semiconductor

FIN1002 LVDS 1-Bit High Speed Differential Receiver February 2002 Revised February 2002 FIN1002 LVDS 1-Bit High Speed Differential Receiver General Description This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 m V, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1002 can be paired with its panion driver, the FIN1001, or with any other LVDS driver. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum pulse skew s 2.5ns maximum propagation delay s Bus pin ESD (HBM) protection exceeds 10k V s Power-Off over voltage tolerant input and output s Fail safe protection for open-circuit and non-driven, shorted or terminated conditions s High impedance output at VCC < 1.5V s Meets or exceeds the TIA/EIA-644 LVDS standard s 5-Lead SOT23 package saves space Ordering Code: Order Number FIN1002M5 FIN1002M5X Package Number MA05B MA05B Package Description 5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel] 5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel] Pin Descriptions Pin Name ROUT RIN+ RIN- VCC GND NC Description LVTTL Data Output Non-inverting Driver Input Inverting Driver Input Power Supply Ground No Connect Connection Diagram Pin Assignment for SOT package Function Table Input RIN+ L H RIN- H L Outputs ROUT L H H Top View Fail Safe Condition H = HIGH Logic Level L = LOW Logic Level Fail Safe = Open, Shorted, Terminated © 2002 Fairchild Semiconductor Corporation DS500730 .fairchildsemi....