FIN1002 Datasheet | onsemi

LVDS 1-Bit, High-Speed Differential Reciever Description This single receiver is designed for high- speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 m V, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high- speed transfer of clock or data. The FIN1002 can be paired with its panion driver, the FIN1001, or with any other LVDS driver. Features - Greater than 400 Mbs Data Rate - 3.3 V Power Supply Operation - 0.4 ns Maximum Pulse Skew - 2.5 ns Maximum Propagation Delay - Bus Pin ESD (HBM) Protection Exceeds 10 k V - Power- Off, Over- voltage Tolerant Input and Output - Fail- safe Protection for open- circuit and Non- driven, Shorted, or Terminated Conditions - High- impedance Output at VCC < 1.5 V - Meets or exceeds TIA/EIA- 644 LVDS Standard - 5- Lead SOT23 Package Saves Space PIN DEFINITIONS Pin No. Function RIN+ RIN- ROUT Description Power Supply Ground for the IC Non- inverting Driver Input Inverting Driver Input LVTTL Data Output FUNCTION TABLE Inputs RIN+ LOW RINHIGH HIGH Fail- Safe Condition (Open, Shorted, Terminated) Outputs ROUT LOW HIGH HIGH DATA SHEET .onsemi. SOT- 23, 5 Lead CASE 527AH MARKING...