programmable delay chip.
http://onsemi.com
PLCC−28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
MCxxxE196FNG AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week.
The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. T.
The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the log.
Image gallery
TAGS
Download (Size : 184.13KB)