5 V ECL Dual Differential
The MC100EL56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple VBB pins are
provided to ease AC coupling input signals.
The VBB pins, an internally generated voltage supply, are available
to this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open, the D input will pull down to VEE. The D input will bias
around VCC/2 forcing the Q output LOW.
• 580 ps Typical Propagation Delays
• Separate and Common Select
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
♦ VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range:
♦ VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
• Q Output will Default LOW with Inputs Open or at VEE
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SOIC−20 wB 1000/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 9
Publication Order Number: