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MC100LVEL12 Datasheet

Low Impedance Driver

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MC100LVEL12
3.3V ECL Low Impedance
Driver
Description
The MC100LVEL12 is a low impedance drive buffer. With two
pairs of OR/NOR outputs the device is ideally suited for high drive
applications such as memory addressing. The device is functionally
equivalent to the EL12 device and operates from a 3.3 V power supply.
With propagation delays equivalent to the EL12, the LVEL12 is
ideally suited for those applications which require the ultimate in
AC performance in a low voltage environment.
Features
445 ps Propagation Delay
Dual Outputs for 25 W Drive Applications
ESD Protection: >4 kV Human Body Model,
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors
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Q Output will Default LOW with All Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 83 devices
PbFree Packages are Available
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
8
1
TSSOP8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KVL12
ALYW
G
1
8
KV12
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 Rev. 3
1
Publication Order Number:
MC100LVEL12/D


  ON Semiconductor Electronic Components Datasheet  

MC100LVEL12 Datasheet

Low Impedance Driver

No Preview Available !

Qa 1
Qb 2
Qa 3
Qb 4
MC100LVEL12
8 VCC
7 D0
6 D1
5 VEE
Table 1. PIN DESCRIPTION
PIN
D0, D1
Qa, Qa; Qb, Qb
VCC
VEE
EP
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI  VCC
VI  VEE
8 to 0
8 to 0
6 to 0
6 to 0
50
100
V
V
V
V
mA
mA
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
40 to +85
65 to +150
190
130
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
8 SOIC
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
41 to 44 ± 5%
185
140
°C/W
°C/W
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
8 TSSOP
qJA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44 ± 5%
129
84
°C/W
°C/W
°C/W
Tsol Wave Solder
Pb <2 to 3 sec @ 248°C
PbFree <2 to 3 sec @ 260°C
265 °C
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
2


Part Number MC100LVEL12
Description Low Impedance Driver
Maker ON Semiconductor
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MC100LVEL12 Datasheet PDF






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