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MC100LVEL13 Datasheet

Dual 1:3 Fanout Buffer

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MC100LVEL13
3.3 V ECL Dual 1:3 Fanout
Buffer
Description
The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer.
The Low Output-Output Skew of the device makes it ideal for
distributing two different frequency synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to VEE, The D input will bias
around VCC/2 and the Q output will go LOW.
Features
500 ps Typical Propagation Delays
50 ps Output-Output Skews
ESD Protection: > 2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 143 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
SOIC20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL13
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping
MC100LVEL13DWG
SOIC20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL13DWR2G SOIC20 WB
(Pb-Free)
1000
Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 7
1
Publication Order Number:
MC100LVEL13/D


  ON Semiconductor Electronic Components Datasheet  

MC100LVEL13 Datasheet

Dual 1:3 Fanout Buffer

No Preview Available !

MC100LVEL13
Q1a Q1a Q2a Q2a VCC Q2b Q2b Q1b Q1b VEE
20 19 18 17 16 15 14 13 12 11
Table 1. PIN DESCRIPTION
PIN FUNCTION
Qna, Qna
Qnb, Qnb
CLKn, CLKn
VCC
VEE
ECL Differential Clock Outputs
ECL Differential Clock Outputs
ECL Differential Clock Inputs
Positive Supply
Negative Supply
1 2 3 4 5 6 7 8 9 10
Q0a Q0a VCC CLKa CLKa CLKb CLKb VCC Q0b Q0b
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
8 to 0
8 to 0
6 to 0
6 to 0
V
V
V
V
Iout Output Current
Continuous
Surge
50 mA
100
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC20 WB
SOIC20 WB
40 to +85
65 to +150
90
60
°C
°C
°C/W
qJC Thermal Resistance (Junction-to-Case)
Standard Board
SOIC20 WB
30 to 35
°C/W
Tsol Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
2


Part Number MC100LVEL13
Description Dual 1:3 Fanout Buffer
Maker ON Semiconductor
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MC100LVEL13 Datasheet PDF






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