MC100LVEL14 Datasheet - ON Semiconductor

MC100LVEL14 1:5 Clock Distribution Chip

The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible .

MC100LVEL14 Features

* a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so tha

MC100LVEL14_ONSemiconductor.pdf