MC100LVEL14 Datasheet PDF - ON Semiconductor 1:5 Clock Distribution Chip Specs

MC100LVEL14 - 1:5 Clock Distribution Chip

Datasheet Summary

Description

designed explicitly for low skew clock distribution applications.

The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal.

Features

a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as ca.

Datasheet Details

Part number	MC100LVEL14
Manufacturer	ON Semiconductor
File Size	138.13 KB
Description	1:5 Clock Distribution Chip
Datasheet	MC100LVEL14 Datasheet
Additional preview pages of the MC100LVEL14 datasheet.

📁 Similar Datasheet

MC100LVEL14 - 1:5 Clock Distribution Chip (Motorola)

MC100LVEL11 - Low Voltage 1:2 Differential Fanout Buffer (Motorola)

MC100LVEL12 - Low Impedance Driver (Motorola)

MC100LVEL13 - Dual 1:3 Fanout Buffer (Motorola)

MC100LVEL16 - Differential Receiver (Motorola)

MC100LVEL17 - Low-Voltage Quad Differential Receiver (Motorola)

MC100LVEL01 - 4-Input OR/NOR (Motorola)

MC100LVEL05 - 2-Input Differential AND/NAND (Motorola)

MC100LVEL29 - Dual Differential Data and Clock D Flip-Flop (Motorola)

MC100LVEL30 - Triple D Flip-Flop (Motorola)

Full PDF Text Transcription

Click to expand full text

MC100LVEL14 3.3 V ECL 1:5 Clock Distribution Chip Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of −3.0 V to −3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.

Published: Apr 26, 2005 |