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  ON Semiconductor Electronic Components Datasheet  

MC100LVEL14 Datasheet

1:5 Clock Distribution Chip

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MC100LVEL14
3.3 V ECL 1:5 Clock
Distribution Chip
Description
The MC100LVEL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to
operate in ECL or PECL mode for a voltage supply range of 3.0 V to
3.8 V ( or 3.0 V to 3.8 V).
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5
mA. When not used, VBB should be left open.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
ESD Protection: Human Body Model > 2 kV
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors on CLK
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 303 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
20
1
SOIC20 WB
DW SUFFIX
CASE 751D05
MARKING DIAGRAM
20
100LVEL14
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
ORDERING INFORMATION
Device
Package Shipping
MC100LVEL14DWG
SOIC20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL14DWR2G SOIC20 WB 1000 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 10
1
Publication Order Number:
MC100LVEL14/D


  ON Semiconductor Electronic Components Datasheet  

MC100LVEL14 Datasheet

1:5 Clock Distribution Chip

No Preview Available !

MC100LVEL14
VCC EN VCC NC SCLK CLK CLK VBB SEL VEE
20 19 18 17 16 15 14 13 12 11
10
D
Q
1 2 3 4 5 6 7 8 9 10
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN FUNCTION
CLK, CLK
ECL Diff Clock Inputs
SCLK
ECL Scan Clock Input
EN ECL Sync Enable
SEL ECL Clock Select Input
Q04, Q04
VBB
VCC
VEE
NC
ECL Diff Clock Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. FUNCTION TABLE
CLK
SCLK
SEL
EN
LX
HX
XL
XH
XX
L
L
H
H
X
L
L
L
L
H
*On next negative transition of CLK or SCLK
X = Don’t Care
Q
L
H
L
H
L*
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
8 to 0
8 to 0
6 to 0
6 to 0
50
100
V
V
V
mA
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC20 WB
SOIC20 WB
±0.5
40 to +85
65 to +150
90
60
mA
°C
°C
°C/W
qJC Thermal Resistance (Junction-to-Case)
Tsol Wave Solder
Standard Board
< 2 to 3 sec @ 260°C
SOIC20 WB
30 to 35
265
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
2


Part Number MC100LVEL14
Description 1:5 Clock Distribution Chip
Maker ON Semiconductor
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MC100LVEL14 Datasheet PDF






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