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  ON Semiconductor Electronic Components Datasheet  

MC14043B Datasheet

CMOS MSI

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MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in
a single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with
a logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
Double Diode Input Protection
Three−State Outputs with Common Enable
Outputs Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation, per Package
(Note 1)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
140xxBG
AWLYWW
1
SOIC−16
16
MC14043B
ALYWG
1
SOEIAJ−16
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1
Publication Order Number:
MC14043B/D


  ON Semiconductor Electronic Components Datasheet  

MC14043B Datasheet

CMOS MSI

No Preview Available !

MC14043B, MC14044B
MC14043B
Q3 1
Q0 2
16 VDD
15 R3
R0 3
14 S3
S0 4
13 NC
E5
12 S2
S1 6
11 R2
R1 7
10 Q2
VSS 8
9 Q1
PIN ASSIGNMENT
MC14044B
Q3 1
NC 2
16 VDD
15 S3
S0 3
14 R3
R0 4
13 Q0
E5
12 R2
R1 6
11 S2
S1 7
10 Q2
VSS 8
9 Q1
NC = NO CONNECTION
MC14043B
4
S0
3
R0
6
S1
7
R1
12
S2
11
R2
14
S3
15
R3
5
ENABLE
MC14044B
2
Q0
4
R0
9
Q1
3
S0
6
R1
10
Q2
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
7
S1
12
R2
1 TRUTH TABLE
Q3 S R E
Q
X X 0 High
Impedance
0 0 1 No Change
011
0
101
1
111
1
X = Don’t Care
11
S2
14
R3
15
S3
5
ENABLE
13
Q0
9
Q1
10
Q2
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
1
Q3
TRUTH TABLE
SRE
Q
X X 0 High
Impedance
001
0
011
1
101
0
1 1 1 No Change
X = Don’t Care
http://onsemi.com
2


Part Number MC14043B
Description CMOS MSI
Maker ON Semiconductor
Total Page 7 Pages
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