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MC74HC112A - Dual J-K Flip-Flop

Features

  • Output Drive Capability: 10 LSTTL Loads.
  • Outputs Directly Interface to CMOS, NMOS, and TTL.
  • Operating Voltage Range: 2.0 to 6.0 V.
  • Low Input Current: 1.0 mA.
  • High Noise Immunity Characteristic of CMOS Devices.
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A.
  • Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously.
  • Chip Complexity: 100 FETs or 25 Equivalent Gates.
  • These.

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Full PDF Text Transcription

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MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has active−low asynchronous Set and Reset inputs. The HC112A is identical in function to the HC76, but has a different pinout. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No.
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