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MTB3N100E Datasheet

High Energy Power FET

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MTB3N100E
Designer’sData Sheet
TMOS E−FET.
High Energy Power FET
D2PAK for Surface Mount
NChannel EnhancementMode Silicon
Gate
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TMOS POWER FET
The D2PAK package has the capability of housing a larger die than
any existing surface mount package which allows it to be used in
applications that require the use of surface mount components with
higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide enhanced
voltageblocking capability without degrading performance over
time. In addition, this advanced TMOS EFET is designed to
withstand high energy in the avalanche and commutation modes. The
new energy efficient design also offers a draintosource diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
3.0 AMPERES, 1000 VOLTS
RDS(on) = 4.0 W
CASE 418B02, Style 2
D2PAK
D
Robust High Voltage Termination
Avalanche Energy Specified
®G
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 3
1
Publication Order Number:
MTB3N100E/D


  ON Semiconductor Electronic Components Datasheet  

MTB3N100E Datasheet

High Energy Power FET

No Preview Available !

MTB3N100E
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
1000
Vdc
DrainGate Voltage (RGS = 1.0 MΩ)
VDGR
1000
Vdc
GateSource Voltage — Continuous
GateSource Voltage — NonRepetitive (tp 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 μs)
ID 3.0 Adc
ID 2.4
IDM 9.0 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD 125 Watts
1.0 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg 55 to 150
°C
Single Pulse DraintoSource Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 7.0 Apk, L = 10 mH, RG = 25 Ω)
EAS 245 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.0 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
EFET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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2


Part Number MTB3N100E
Description High Energy Power FET
Maker ON Semiconductor
Total Page 11 Pages
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