clock oscillator.
http://onsemi.com MARKING DIAGRAMS
NBXDBA019 125/250 AWLYYWWG
6 PIN CLCC LN SUFFIX CASE 848AB
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LVPECL Differential.
The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 125 MHz or 250 .
LVTTL/LVCMOS Control Input LVTTL/LVCMOS Control Input Power Supply Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. FSEL/ NC* GND CLK CLK VDD Output Frequency Select Pin. Pin will .
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