clock oscillator.
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6 PIN CLCC LN SUFFIX CASE 848AB
MARKING DIAGRAMS
NBXDDB016 133.33/137.93 AWLYYWWG NBXDDA016 133.33/137.93 AWLYYWWG
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The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 133.33 MHz or 1.
Pin No. 1 2 3 4 5 6 Symbol OE FSEL GND CLK CLK VDD I/O LVTTL/LVCMOS Control Input Control Input Power Supply CML Output CML Output Power Supply Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE .
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