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NL17SH17 - Single Schmitt-Trigger Buffer

Key Features

  • High Speed: tPD = 4.0 ns (Typ) at VCC = 5.0 V.
  • Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C.
  • Power Down Protection Provided on Inputs.
  • Balanced Propagation Delays.
  • Pin and Function Compatible with Other Standard Logic Families.
  • Chip Complexity: FETs = 101.
  • These Devices are Pb.
  • Free and are RoHS Compliant IN A 1 5 VCC http://onsemi. com.

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Datasheet Details

Part number NL17SH17
Manufacturer onsemi
File Size 94.82 KB
Description Single Schmitt-Trigger Buffer
Datasheet download datasheet NL17SH17 Datasheet

Full PDF Text Transcription for NL17SH17 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NL17SH17. For precise diagrams, and layout, please refer to the original PDF.

NL17SH17 Single Schmitt-Trigger Buffer The NL17SH17 is a single gate CMOS Schmitt−trigger non−inverting buffer fabricated with silicon gate CMOS technology. The internal ...

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ing buffer fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The NL17SH17 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the NL17SH17 to be used to interface 5 V circuits to 3 V circuits. The NL17SH17 can be used to enhance noise immunity or to square up slowly changing waveforms. Features • High Speed: tPD = 4.0 ns (Typ) at VCC = 5.0 V • Low Power Dissipation: ICC = 1.