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  ON Semiconductor Electronic Components Datasheet  

SN74LS374 Datasheet

Octal Transparent Latch

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SN74LS373, SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC
TA
Supply Voltage
Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
–2.6 mA
24 mA
20
1
http://onsemi.com
LOW
POWER
SCHOTTKY
MARKING
DIAGRAMS
SN74LS37xN
AWLYYWW
1
PDIP–20
N SUFFIX
CASE 738
20
1
LS37x
AWLYYWW
1
SOIC–20
DW SUFFIX
CASE 751D
74LS37x
AWLYWW
20
1 SOEIAJ–20 1
M SUFFIX
CASE 967
x = 3 or 4
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 8
1
Publication Order Number:
SN74LS373/D


  ON Semiconductor Electronic Components Datasheet  

SN74LS374 Datasheet

Octal Transparent Latch

No Preview Available !

SN74LS373, SN74LS374
CONNECTION DIAGRAM DIP (TOP VIEW)
SN74LS373
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
SN74LS374
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE
O0
D0
D1
O1
O2
D2
D3
O3 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual InĆLine Package.
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
PIN NAMES
D0 - D7
LE
CP
OE
O0 - O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
NOTES:
ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
LS373
TRUTH TABLE
Dn LE OE On
H H LH
Dn
H
L H LL
L
X LL
X XH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Q0
Z*
X
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LS374
LE OE
L
L
XH
On
H
L
Z*
http://onsemi.com
2


Part Number SN74LS374
Description Octal Transparent Latch
Maker ON Semiconductor
Total Page 8 Pages
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