Description
2 system level description
2.1 overview 2.2 architecture 2.3 video timing overview 2.4 pixel array addresses 2.5 mirror and flip 2.6 format and frame rate control 2.7 integration time control (electronic shutter control) 2.8 black level calibration 2.9 PLL and clock generator 2.10 MIPI interface 3
Features
- MIPI and D-PHY specification (contains one clock lane) with a maximum of 750 Mbps data transfer rate
support for output formats: 10-bit RAW RGB
programmable controls for frame rate, mirror and flip, cropping, and windowing
low operating voltage and low power consumption for embedded portable.