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PM5309 - Multi-rate Telecom Backplane SERDES

Download the PM5309 datasheet PDF. This datasheet also covers the PM5309_PMC variant, as both devices belong to the same multi-rate telecom backplane serdes family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High performance backplane interface and cross-connect for 2.5G line cards in SONET/SDH systems.
  • Provides one low-speed parallel TelecomBus interface operating at 32 bits x 77.76 MHz.
  • Provides three high-speed multi-rate serial backplane interfaces.
  • Supports CLOS and memory-based switch fabric systems.
  • Supports linear, UPSR, and BLSR protection strategies.
  • Provides two pages of connection memory with software and hardware controlled hit.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PM5309_PMC-Sierra.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PM5309
Manufacturer PMC-Sierra
File Size 65.35 KB
Description Multi-rate Telecom Backplane SERDES
Datasheet download datasheet PM5309 Datasheet

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Other Datasheets by PMC-Sierra

Part Number Description
PM5307 9.953 Gbit/s Telecom Bus Serializer
PM5310 TelecomBus Serializer
PM5312 SONET/SDH TRANSPORT TERMINATING TRANSCEIVER
PM5313 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
PM5315 SONET/SDH Payload Extractor/Aligner

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Released PM5309 TBS 2488 Multi-rate Telecom Backplane SERDES for 2.5 Gbit/s Interconnect FEATURES • High performance backplane interface and cross-connect for 2.5G line cards in SONET/SDH systems. • Provides one low-speed parallel TelecomBus interface operating at 32 bits x 77.76 MHz. • Provides three high-speed multi-rate serial backplane interfaces. • Supports CLOS and memory-based switch fabric systems. • Supports linear, UPSR, and BLSR protection strategies. • Provides two pages of connection memory with software and hardware controlled hitless page swaps at frame boundaries. • Provides integrated delay management that allows for arbitrary SONET/SDH frame alignments on each ingress serial link. • High-speed serial RASIO compatible with CML, LVDS, and LVPECL.