Datasheet4U Logo Datasheet4U.com

PM5377 - Single Chip 96-Port STS-1/STM-0 Cross-Connect

Download the PM5377 datasheet PDF. This datasheet also covers the PM5377_PMC variant, as both devices belong to the same single chip 96-port sts-1/stm-0 cross-connect family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity.
  • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single device.
  • Supports a single-stage, anycast switching capacity of 240G. DELAY.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PM5377_PMC-Sierra.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PM5377
Manufacturer PMC-Sierra
File Size 58.02 KB
Description Single Chip 96-Port STS-1/STM-0 Cross-Connect
Datasheet download datasheet PM5377 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PM5324 HF Generator Philips
PM503BA P-Channel MOSFET UNIKC
PM50502C Silicon N-Channel MOS Type FET HITACHI
PM505BA P-Channel MOSFET UNIKC
PM505BA P-Channel Field Effect Transistor NIKO-SEM

Other Datasheets by PMC-Sierra

Part Number Description
PM5371 SONET/SDH TRIBUTARY UNIT CROSS CONNECT
PM5372 40 Gbit/s Transport Switching Element
PM5307 9.953 Gbit/s Telecom Bus Serializer
PM5309 Multi-rate Telecom Backplane SERDES
PM5310 TelecomBus Serializer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect FEATURES • Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. • 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single device. • Supports a single-stage, anycast switching capacity of 240G. DELAY MANAGEMENT • Provides a 108 byte FIFO for each ingress port to support 102 byte maximum skew among the input links (1312 ns for 622 Mbit/s links and 328 ns for 2.488 Gbit/s links). • Provides 13 delay management (DM) blocks that can be allocated to a subset of devices ports (1 through 25) as either input delay management (DMI) or output delay management (DMO).