MN8390-C Datasheet | Panasonic

Overview The MN8390-C is for displaying an analog video signal on a TFT color liquid crystal display panel in such applications as LCD television sets and video cameras. Features Lower power consumption and reduced EMI emissions owing to digital 3.0 volt power supply and analog 5.0 volt power supply Broad dynamic range of 4.6 V (for power supply voltage of 5.0 V) Low discrepancies between output pins: ±20 m V (typ.) 240 output channels Support for striped and delta panel layouts by switching analog (R, G, B) signals Support for sequential sampling mode (with CLK1 to CLK3 inputs) Support for serial cascade connections Automatic clock suspension after reading specified amount of data Choice of shift register shift directions (right/left) Applications LCD television sets and video cameras For Information Equipment Block Diagram QA80 QB80 QC80 STHL QA1 QB1 QC1 VDD2 VSS2 VBS OE Bias control circuit Output buffer 240 VA,VB, VC D1 VDD1 VSS1 240 Clock generator circuit Analog multiplexer Two sample-and-hold circuits CLK1, CLK2, CLK3 Bidirectional 240-bit shift register MOD RL STHR TEST1 TEST2 Shift register control circuit For Information Equipment Pin Descriptions Pin No. 99 to 102 21 to 24 Symbol STHR STHL Pin Name Shift data I/O I/O I/O Function Description These are I/O pins for the bidirectional shift register. The RL pin controls their I/O directions. RL H L STHR Input Output STHL Output Input 27 to 30 Shift direction control (1) Input The pins provide input data to the shift register's first stage. The shift register reads in this data at the rising edge of the CLK1 signal. (2) Output In a cascade connection, the pins provide the data for the synchronizing output stage synchronized with the rising edge of the CLK1 signal. This pin controls the shift direction for the bidirectional shift register. RL="H" : QA1 → QB1 → QC1→ → QC80 RL="L" : QC80 → QB80→ QA80→ → QA1 42 to 45 37 to 40 32 to 35 CLK1 to 3 Clock...