900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Peregrine Semiconductor

PE3336 Datasheet Preview

PE3336 Datasheet

Integer-N PLL

No Preview Available !

Product Description
Peregrine’s PE3336 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3336 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
The PE3336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE3336 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
Product Specification
PE3336
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Features
3000 MHz operation
÷10/11 dual modulus prescaler
Internal phase detector
Serial, parallel or hardwired
programmable
Pin compatible with PE3236
Ultra-low phase noise
Available in 44-lead PLCC and
7x7 mm 48-lead QFN package
Figure 1. Block Diagram
Fin
www.DaFtaiSn heet4U.com
Prescaler
10 / 11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
Phase
Detector
PD_U
PD_D
fc
Document No. 70-0033-02 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15




Peregrine Semiconductor

PE3336 Datasheet Preview

PE3336 Datasheet

Integer-N PLL

No Preview Available !

PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
(44-lead PLCC) (48-lead QFN)
Pin
Name
Interface
Mode
Type
S_WR
Serial
Input
13 7
D4
Parallel
Input
M4
Direct
Input
Sdata
Serial
Input
14
8 D5
Parallel
Input
M5
Direct
Input
Sclk
Serial
Input
15 9
D6
Parallel
Input
M6
Direct
Input
FSELS
Serial
Input
16
10 D7
Parallel
Input
Pre_en
Direct
Input
17
11
GND
ALL
FSELP
Parallel
Input
18 12
A0
Direct
Input
www.DataSheet4U.com
19
13
20 14
21 15
22 16
23 17,18
24 19
E_WR
A1
M2_WR
A2
Smode
A3
Bmode
VDD
M1_WR
Serial
Parallel
Direct
Parallel
Direct
Serial,
Parallel
Direct
ALL
ALL
Parallel
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
25
20
A_WR
Parallel
Input
26
21
Hop_WR
Serial,
Parallel
Input
27
22 Fin
ALL Input
Description
Serial load enable input. While S_WR is “low”, Sdata can be
serially clocked. Primary register data are transferred to the
secondary register on S_WR or Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit
primary register (E_WR “low”) or the 8-bit enhancement
register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary
register (FSELS=0) for programming of internal counters while
in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, Fin bypasses the
prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary
register (FSELP=0) for programming of internal counters while
in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”,
Sdata can be serially clocked into the enhancement register
on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the
enhancement register on the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M
[8:7]) on the rising edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or
Parallel Interface Mode (Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on the rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A
[3:0]) on the rising edge of A_WR.
Hop write. The contents of the primary register are latched
into the secondary register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Document No. 70-0033-02 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15


Part Number PE3336
Description Integer-N PLL
Maker Peregrine Semiconductor
Total Page 15 Pages
PDF Download

PE3336 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 PE3335 Integer-N PLL
Peregrine Semiconductor
2 PE3336 Integer-N PLL
Peregrine Semiconductor
3 PE3339 Integer-N PLL
Peregrine Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy