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Peregrine Semiconductor

PE4230 Datasheet Preview

PE4230 Datasheet

SPDT High Power UltraCMOS RF Switch

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Product Description
The PE4230 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from DC through 3000 MHz. This
single-supply reflective switch integrates on-board CMOS
control logic driven by a simple, single-pin CMOS or TTL
compatible control input. Using a nominal +3-volt power supply,
a typical input 1 dB compression point of +32 dBm can be
achieved. The PE4230 also exhibits input-output isolation of
better than 39 dB at 1000 MHz and is offered in a small 8-lead
MSOP package.
The PE4230 SPDT High Power UltraCMOS™ RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
Product Specification
PE4230
SPDT High Power UltraCMOS™
RF Switch
Features
Single 3-volt power supply
Low insertion loss: 0.35 dB at
1000 MHz, 0.55 dB at 2000 MHz
High isolation of 39 dB at 1000 MHz,
30 dB at 2000 MHz
Typical input 1 dB compression point
of +32 dBm
Single-pin CMOS or TTL logic control
Low cost
Figure 2. Package Type
8-lead MSOP
RF1 RF2
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 )
Parameter
Conditions
Minimum
Typical
Maximum
Units
Operation Frequency1
DC
3000
MHz
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
0.35 0.45
0.55 0.65
38 39
28 30
33.5 35
26.5
23.5
28
25.5
14.5 15.4
dB
dB
dB
dB
dB
dB
dB
dB
‘ON’ Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
‘OFF’ Switching Time
CTRL to 25 dB isolation, 2 GHz
90 ns
Video Feedthrough2
Input 1 dB Compression
2000 MHz
15
30 32
mVpp
dBm
Input IP3
2000 MHz, 17 dBm
50
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
dBm
Document No. 70-0029-02 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7




Peregrine Semiconductor

PE4230 Datasheet Preview

PE4230 Datasheet

SPDT High Power UltraCMOS RF Switch

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Figure 3. Pin Configuration (Top View)
VDD 1
CTRL 2
GND 3
RFC 4
4230
8 RF1
7 GND
6 GND
5 RF2
Table 2. Pin Descriptions
Pin Pin
No. Name
Description
1 VDD Nominal +3V supply connection.
2
CTRL
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
4
RFC
Common RF port for switch.1
5 RF2 RF2 port.1
6
GND
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
7
GND
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
8 RF1 RF1 port.1
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 VDC.
Table 3. DC Electrical Specifications
Parameter
Min Typ Max
Units
VDD Power Supply Voltage
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V)
Control Voltage High
Control Voltage Low
2.7 3.0
29
0.7xVDD
3.3
35
0.3xVDD
V
µA
V
V
PE4230
Product Specification
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
VI
VCTRL
TST
TOP
PIN
VESD
Power supply voltage
Voltage on any input
except for the CTRL input
-0.3 4.0
-0.3
VDD+
0.3
V
V
Voltage on CTRL input
5.0 V
Storage temperature range -65 150
°C
Operating temperature
range
Input power (50)
-40 85
°C
35 dBm
ESD voltage (Human Body
Model)
250 V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
CTRL = CMOS or TTL High
RFC to RF1
CTRL = CMOS or TTL Low
RFC to RF2
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic driv-
ers, the control logic input has been designed to
handle a 5-volt logic HIGH signal. (A minimal cur-
rent will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0029-02 UltraCMOS™ RFIC Solutions


Part Number PE4230
Description SPDT High Power UltraCMOS RF Switch
Maker Peregrine Semiconductor
Total Page 7 Pages
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