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Peregrine Semiconductor

PE4231 Datasheet Preview

PE4231 Datasheet

SPDT High Power UltraCMOS

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Product Description
The PE4231 SPDT High Power UltraCMOS™ RF Switch is
designed to cover a broad range of applications from DC to 1.3
GHz. This single-supply reflective switch integrates on-board
CMOS control logic driven by a simple, single-pin CMOS or
TTL compatible control input. Using a nominal +3-volt power
supply, a typical input 1 dB compression point of +32 dBm can
be achieved. The PE4231 also exhibits input-output isolation of
better than 42 dB at 1.0 GHz and is offered in a small 8-lead
MSOP package.
The PE4231 SPDT High Power UltraCMOS™ RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Product Specification
PE4231
SPDT High Power UltraCMOS™
DC – 1.3 GHz RF Switch
Features
Optimized for 75 systems
Single +3-volt power supply
Low insertion loss: 0.80 dB at 1.0 GHz
High isolation: 42 dB at 1.0 GHz
Typical input 1 dB compression point of
+32 dBm
Single-pin CMOS or TTL logic control
Low cost
Figure 1. Functional Diagram
RFCommon
Figure 2. Package Type
8-lead MSOP
RF1 RF2
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 75 )
Parameter
Operation Frequency1
Insertion Loss
Isolation – RFCommon to
RF1/RF2
Isolation – RF1 to RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough2
Input 1 dB Compression3
Input IP33
Conditions
50 MHz
1000 MHz
50 MHz
1000 MHz
50 MHz
1000 MHz
1000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
1000 MHz
1000 MHz, 17 dBm
Minimum
DC
73
40
58
33
16
30
50
Typical
0.50
0.80
75
42
60
35
17
2000
900
15
32
Maximum
1300
0.60
0.90
Units
MHz
dB
dB
dB
dB
ns
ns
mVpp
dBm
dBm
Notes:
1. Device linearity will begin to degrade below 1 MHz.
2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
3. Measured in a 50 system.
Document No. 70-0097-01 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7




Peregrine Semiconductor

PE4231 Datasheet Preview

PE4231 Datasheet

SPDT High Power UltraCMOS

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Figure 3. Pin Configuration (Top View)
VDD 1
CTRL 2
GND 3
RFCommon 4
4231
8 RF1
7 GND
6 GND
5 RF2
Table 2. Pin Descriptions
Pin
No.
Pin Name
Description
1 VDD Nominal +3 V supply connection.
2
CTRL
CMOS or TTL logic level:
High = RFCommon to RF1 signal path
Low = RFCommon to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
4 RF Common Common RF port for switch.1
5 RF2 RF2 port.1
6
GND
Ground Connection. Traces should be
physically short and connected to ground
7
GND
Ground Connection. Traces should be
physically short and connected to ground
8 RF1 RF1 port.1
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 VDC.
Table 3. Absolute Maximum Ratings
Symbol
VDD
VI
VCTRL
TST
TOP
PIN
VESD
Parameter/
Conditions
Power supply voltage
Voltage on any input ex-
cept for the CTRL input
Voltage on CTRL input
Storage temperature
range
Operating temperature
range
Input power (50)
ESD voltage (Human
Body Model)
Min Max
-0.3 4.0
-0.3
VDD+
0.3
5.0
-65 150
-40 85
33
200
Units
V
V
V
°C
°C
dBm
V
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
PE4231
Product Specification
Table 4. DC Electrical Specifications
Parameter
Min Typ Max
VDD Power Supply
Voltage
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V)
Control Voltage High
2.7
0.7xVDD
3.0
29
3.3
35
Units
V
µA
V
Control Voltage Low
0.3xVDD
V
Table 5. Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFCommon to RF1
RFCommon to RF2
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Document No. 70-0097-01 UltraCMOS™ RFIC Solutions


Part Number PE4231
Description SPDT High Power UltraCMOS
Maker Peregrine Semiconductor
Total Page 7 Pages
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